In the semiconductor industry, the fabrication of integrated circuits (IC) can be divided at least into three phases: wafer fabrication, IC fabrication process, and IC packaging. Each chip is fabricated through wafer fabrication, circuit design, photolithography and etching processes, and wafer dicing. After each chip formed based on the wafer dicing is electrically connected to external signals through a bonding pad on the chip, the chip can be encapsulated by a sealant material. The packaging process protects the chip from heat, humidity, and noises and provides an electrical connection medium between the chip and external circuits. By such means, packaging of the IC is completed.
Mobile devices such as mobile phones, mobile internet devices (MIDs) and laptops, are designed with smaller form factor and slimmer profile for improved aesthetic and functional appeals. The size of and real estate occupied by semiconductor packages in the devices need to be scaled down accordingly. Package-on-package (PoP) packaging technology is employed to stack a semiconductor package on top of another semiconductor package to remove the x and y dimensions constraints in the layout of semiconductor packages on a motherboard. PoP allows vertically combining, for example, discrete logic and memory ball grid array (BGA) packages. Two or more packages are installed on top of one another, e.g. stacked, with a standard interface to route signals between them. This allows higher density in the mobile device market.
Today's PoP semiconductor devices enjoy increasing popularity, because they promise to use components already developed and thus quickly available, they are supposed to retain a slim space-saving contour after assembly, and they are expected to be robust in terms of reliability in use-test under variable temperature and moisture conditions.